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0.1 C 6 ghz 3 v, 14 dbm amplifier technical data features ? lead-free option available ? +14.8 dbm p 1db at 2.0 ghz +17 dbm p sat at 2.0 ghz ? single +3v supply ? 2.8 db noise figure at 2.0 ghz ? 12.4 db gain at 2.0 ghz ? ultra-miniature package ? unconditionally stable applications ? buffer or driver amp for pcs, phs, ism, satcom and wll applications ? high dynamic range lna mga-81563 description agilents mga-81563 is an eco- nomical, easy-to-use gaas mmic amplifier that offers excellent power and low noise figure for applications from 0.1 to 6 ghz. packaged in an ultra-miniature sot-363 package, it requires half the board space of a sot-143 package. the output of the amplifier is matched to 50 ? (better than 2.1:1 vswr) across the entire bandwidth. the input is partially matched to 50 ? (better than 2.5:1 vswr) below 4 ghz and fully matched to 50 ? (better than 2:1 vswr) above. a simple series inductor can be added to the input to improve the input match below 4 ghz. the amplifier allows a wide dynamic range by offering a 2.7 db nf coupled with a +27 dbm output ip 3 . the circuit uses state-of-the-art phemt technology with proven reliability. on-chip bias circuitry allows operation from a single +3 v power supply, while resistive feedback ensures stability (k>1) over all frequencies and temperatures. surface mount package sot-363 (sc-70) pin connections and package marking output and v d gnd 81 gnd gnd input 1 2 3 6 5 4gnd note: package marking provides orientation and identification. simplified schematic input 3 output and v d 6 gnd bias 1, 2, 4, 5 bias attention: observe precautions for handling electrostatic sensitive devices. esd machine model (class a) esd human body model (class 0) refer to agilent application note a004r: electrostatic discharge damage and control.
2 thermal resistance [2] : ch-c = 220 c/w notes: 1. permanent damage may occur if any of these limits are exceeded. 2. t c = 25 c (t c is defined to be the temperature at the package pins where contact is made to the circuit board.) mga-81563 electrical specifications, t c = 25 c, z o = 50 ? , v d = 3 v symbol parameters and test conditions units min. typ. max. std dev [2] g test gain in test circuit [1] f = 2.0 ghz 10.5 12.4 14.5 0.44 nf test noise figure in test circuit [1] f = 2.0 ghz 2.8 3.8 0.21 nf 50 noise figure in 50 ? system f = 0.5 ghz db 3.1 f = 1.0 ghz 3.0 f = 2.0 ghz 2.7 0.21 f = 3.0 ghz 2.7 f = 4.0 ghz 2.8 f = 6.0 ghz 3.5 |s 21 | 2 gain in 50 ? system f = 0.5 ghz db 12.5 f = 1.0 ghz 12.5 f = 2.0 ghz 12.3 0.44 f = 3.0 ghz 11.8 f = 4.0 ghz 11.4 f = 6.0 ghz 10.2 p 1 db output power at 1 db gain compression f = 0.5 ghz dbm 15.1 f = 1.0 ghz 14.8 f = 2.0 ghz 14.8 0.86 f = 3.0 ghz 14.8 f = 4.0 ghz 14.8 f = 6.0 ghz 14.7 ip 3 output third order intercept point f = 2.0 ghz dbm +27 1.0 vswr in input vswr f = 2.0 ghz 2.7:1 vswr out output vswr f = 2.0 ghz 2.0:1 i d device current ma 31 42 51 notes: 1. guaranteed specifications are 100% tested in the circuit in figure 10 in the applications information section. 2. standard deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical specification. mga-81563 absolute maximum ratings absolute symbol parameter units maximum [1] v d device voltage, rf output v 6.0 to ground v gd device voltage, gate v -6.0 to drain v in range of rf input voltage v +0.5 to -1.0 to ground p in cw rf input power dbm +13 t ch channel temperature c 165 t stg storage temperature c -65 to 150
3 mga-81563 typical performance , t c = 25 c, v d = 3 v 0345 12 6 0 345 12 6 frequency (ghz) frequency (ghz) figure 2. noise figure (into 50 ? ) vs. frequency and temperature. t a = +85 c t a = +25 c t a = ?0 c 0 2 4 6 8 16 12 14 10 gain (db) 0 1 2 3 4 5 noise figure (db) t a = +85 c t a = +25 c t a = ?0 c figure 1. 50 ? power gain vs. frequency and temperature. 0345 12 6 frequency (ghz) figure 3. output power @ 1 db gain compression vs. frequency and temperature. p 1 db (dbm) 11 12 13 14 15 16 t a = +85 c t a = +25 c t a = ?0 c 0 1 2 3 4 5 0345 12 6 noise figure (db) frequency (ghz) figure 5. noise figure (into 50 ? ) vs. frequency and voltage. v d = 3.3v v d = 3.0v v d = 2.7v 11 12 13 14 15 16 0345 12 6 frequency (ghz) figure 6. output power @ 1 db gain compression) vs. frequency and voltage. p 1 db (dbm) v d = 3.3v v d = 3.0v v d = 2.7v 0 2 4 6 8 16 12 14 10 0345 12 6 gain (db) frequency (ghz) figure 4. 50 ? power gain vs. frequency and voltage. v d = 3.3v v d = 3.0v v d = 2.7v 0345 12 6 vswr (n:1) frequency (ghz) figure 7. input and output vswr into 50 ? vs. frequency. 1 1.5 2 3 2.5 4 3.5 0345 12 0 10 20 40 30 60 50 device current (ma) device voltage (v) figure 8. device current vs. voltage and temperature. frequency (ghz) figure 9. minimum noise figure and associated gain vs. frequency. gain and nf (db) t a = +85 c t a = +25 c t a = -40 c nf gain 0345 12 6 0 2 4 6 8 16 12 14 10 input output
4 mga-81563 typical scattering parameters [1] , t c = 25 c, z o = 50 ? , v d = 3 v freq. s 11 s 21 s 12 s 22 k ghz mag ang db mag ang db mag ang mag ang factor 0.1 0.57 -16 13.02 4.48 172 -25 0.051 312 0.43 -14 1.47 0.2 0.52 -13 12.58 4.258 171 -25 0.057 17 0.38 -13 1.58 0.5 0.49 -16 12.35 4.15 164 -25 0.059 8 0.35 -9 1.64 1.0 0.48 -28 12.18 4.06 152 -25 0.061 5 0.35 -15 1.65 1.5 0.47 -40 12.00 3.98 140 -25 0.063 5 0.34 -22 1.65 2.0 0.45 -52 11.82 3.90 128 -24 0.067 4 0.34 -30 1.65 2.5 0.43 -63 11.63 3.81 116 -24 0.070 2 0.32 -39 1.66 3.0 0.39 -75 11.37 3.70 104 -24 0.074 -1 0.31 -46 1.69 3.5 0.35 -87 11.11 3.59 93 -22 0.077 -4 0.29 -53 1.73 4.0 0.32 -100 10.85 3.49 81 -22 0.081 -7 0.27 -60 1.77 4.5 0.28 -114 10.58 3.38 70 -22 0.083 -11 0.25 -67 1.82 5.0 0.25 -130 10.30 3.27 59 -21 0.087 -15 0.23 -74 1.85 5.5 0.22 -146 10.02 3.17 49 -21 0.09 -20 0.21 -81 1.91 6.0 0.20 -166 9.75 3.07 38 -21 0.091 -25 0.19 -90 1.93 6.5 0.18 174 9.46 2.97 27 -21 0.093 -30 0.17 -96 1.98 7.0 0.17 150 9.12 2.86 16 -21 0.094 -36 0.14 -100 2.05 mga-81563 typical noise parameters [1] t c = 25 c, z o = 50 ? , v d = 3 v frequency nf o opt r n / 50 ? ghz db mag. ang. 0.5 2.90 0.16 1 1.57 1.0 2.80 0.15 17 0.96 1.5 2.70 0.14 28 0.75 2.0 2.69 0.14 37 0.41 2.5 2.68 0.13 44 0.39 3.0 2.68 0.11 50 0.38 3.5 2.68 0.09 56 0.36 4.0 2.69 0.06 65 0.34 4.5 2.69 0.03 76 0.33 5.0 2.68 0.01 137 0.32 5.5 2.67 0.02 -135 0.32 6.0 2.67 0.05 -109 0.32 6.5 2.71 0.07 -95 0.33 7.0 2.77 0.09 -78 0.36 note: 1. reference plane per figure 11 in applications information section.
5 mga-81563 applications information introduction this high performance gaas mmic amplifier was developed for commercial wireless applications from 100 mhz to 6 ghz. the mga-81563 runs on only 3 volts and typically requires only 42 ma to deliver 14.8 dbm of output power at 1 db gain compression. an innovative internal bias circuit regulates the devices internal current to enable the mga-81563 to operate over a wide tempera- ture range with a single, positive power supply of 3 volts. the mga-81563 will operate with reduced performance with voltages as low as 1.5 volts. the mga-81563 uses resistive feedback to simultaneously achieve flat gain over a wide bandwidth and match the input and output impedances to 50 ? . the mga-81563 is unconditionally stable (k>1) over its entire frequency range, making it both very easy to use and yielding consistent performance in the manufacture of high volume wireless products. with a combination of high linearity (+27 dbm output ip 3 ) and low noise figure (3 db), the mga-81563 offers outstanding performance for applications requiring a high dynamic range, such as receivers operating in dense signal environments. a wide dynamic range amplifier such as the mga-81563 can often be used to relieve the requirements of bulky, lossy filters at a receivers input. the 14.8 dbm output power (p 1db ) also makes the mga-81563 extremely useful for pre-driver, driver and buffer stages. for transmitter gain stage applications that require higher output power, the mga-81563 can provide 50 mw (17 dbm) of saturated output power with a high power added efficiency of 45%. test circuit the circuit shown in figure 10 is used for 100% rf testing of noise figure and gain. the 3.9 nh inductor at the input fix-tunes the circuit to 2 ghz. the only purpose of the rfc at the output is to apply dc bias to the device under test. tests in this circuit are used to guarantee the nf test and g test parameters shown in the table of electrical specifications. rf input 3.9 nh 22 nh rfc 100 pf 100 pf vd rf output 81 figure 10. test circuit. phase reference planes the positions of the reference planes used to specify the s- parameters and noise parameters for this device are shown in figure 11. as seen in the illustra- tion, the reference planes are located at the point where the package leads contact the test circuit. test circuit reference planes figure 11. phase reference planes. specifications and statistical parameters several categories of parameters appear within this data sheet. parameters may be described with values that are either minimum or maximum, typical, or standard deviations. the values for parameters are based on comprehensive product characterization data, in which automated measurements are made on of a minimum of 500 parts taken from 3 non- consecutive process lots of semiconductor wafers. the data derived from product character- ization tends to be normally distributed, e.g., fits the standard bell curve. parameters considered to be the most important to system perfor- mance are bounded by minimum or maximum values. for the mga-81563, these parameters are: gain (g test ), noise figure (nf test ), and device current (i d ). each of these guaranteed parameters is 100% tested. values for most of the parameters in the table of electrical specifica- tions that are described by typical data are the mathematical mean ( ), of the normal distribution taken from the characterization data. for parameters where measurements or mathematical averaging may not be practical, such as the noise and s-parameter tables or performance curves, the data represents a nominal part taken from the center of the characterization distribution. typical values are intended to be used as a basis for electrical design.
6 to assist designers in optimizing not only the immediate circuit using the mga-81563, but to also optimize and evaluate trade-offs that affect a complete wireless system, the standard deviation ( ) is provided for many of the electrical specifica- tions parameters (at 25 ) in addition to the mean. the stan- dard deviation is a measure of the variability about the mean. it will be recalled that a normal distribu- tion is completely described by the mean and standard deviation. standard statistics tables or calculations provide the probabil- ity of a parameter falling between any two values, usually symmetri- cally located about the mean. referring to figure 12 for ex- ample, the probability of a param- eter being between 1 is 68.3%; between 2 is 95.4%; and be- tween 3 is 99.7%. 68% 95% 99% parameter value mean ( ) (typical) -3 -2 -1 +1 +2 +3 figure 12. normal distribution. rf layout the rf layout in figure 13 is suggested as a starting point for microstripline designs using the mga-81563 amplifier. adequate grounding is needed to obtain optimum performance and to maintain stability. all of the ground pins of the mmic should be connected to the rf groundplane on the backside of the pcb by means of plated through holes (vias) that are placed near the package termi- nals. as a minimum, one via should be located next to each ground pin to ensure good rf grounding. it is a good practice to use multiple vias to further minimize ground path inductance. 81 50 ? 50 ? rf input rf output and v d figure 13. rf layout. it is recommended that the pcb pads for the ground pins not be connected together underneath the body of the package. pcb traces hidden under the package cannot be adequately inspected for smt solder quality. pcb material fr-4 or g-10 printed circuit board materials are a good choice for most low cost wireless applica- tions. typical board thickness is 0.020 to 0.031 inches. the width of the 50 ? microstriplines on pc boards in this thickness range is also very convenient for mounting chip components such as the series inductor at the input or dc blocking and bypass capacitors. for higher frequencies or for noise figure critical applications, the additional cost of ptfe/glass dielectric materials may be warranted to minimize transmis- sion line loss at the amplifiers input. a 0.5 inch length of 50 ? microstripline on fr-4, for example, has approximately 0.3 db loss at 4 ghz. this loss will add directly to the noise figure of the mga-81563. biasing the mga-81563 is a voltage- biased device and is designed to operate from a single, +3 volt power supply with a typical current drain of 42 ma. the internal current regulation circuit allows the amplifier to be oper- ated with voltages as high +5 volts or as low as +1.5 volt. refer to the section titled operation at bias voltages other than 3 volts for information on performance and precautions when using other voltages. typical application example the printed circuit layout in figure 14 can serve as a design guide. this layout is a microstripline design (solid groundplane on the backside of the circuit board) with a 50 ? input and output. the circuit is fabricated on 0.031-inch thick fr-4 dielectric material. plated through holes (vias) are used to bring the ground to the top side of the circuit where needed. multiple vias are used to reduce the inductance of the paths to ground. in out +v mga-8-a figure 14. pcb layout. a schematic diagram of the application circuit is shown in figure 15. dc blocking capacitors (c1 and c2) are used at the input and output of the mmic to isolate the device from adjacent circuits.
7 although the input terminal of the mga-81563 is at ground potential, it is not a current sink. if the input is connected to a preceding stage that has a voltage present, the use of the dc blocking capacitor (c1) is required. c2 c2 c4 c1 l1 rfc v d rf output rf input figure 15. schematic diagram. dc bias is applied to the mga- 81563 through the rf output pin. an inductor (rfc), or length of high impedance transmission line (preferably /4 at the band center), is used to isolate the rf from the dc supply. the power supply is bypassed to ground with capacitor c3 to keep rf off of the dc lines and to prevent gain dips or peaks in the response of the amplifier. an additional bypass capacitor, c4, may be added to the bias line near the v d connection to elimi- nate unwanted feedback through bias lines that could cause oscilla- tion. c4 will not normally be needed unless several stages are cascaded using a common power supply. when multiple bypass capacitors are used, consideration should be given to potential resonances. it is important to ensure that the capacitors when combined with additional parasitic ls and cs on the circuit board do not form resonant circuits. the addition of a small value resistor in the bias supply line between bypass capacitors will often de-q the bias circuit and eliminate the effect of a resonance. the value of the dc blocking and rf bypass capacitors (c1 C c3) should be chosen to provide a small reactance (typically < 5 ohms) at the lowest operating frequency. the reactance of the rf choke (rfc) should be high (e.g., several hundred ohms) at the lowest frequency of operation. the mga-81563s response at low frequencies is limited to approxi- mately 100 mhz by the size of capacitors integrated on the mmic chip. the input of the mga-81563 is partially matched internally to 50 ? . without external matching elements, the input vswr of the mga-81563 is 3.0:1 at 300 mhz and decreases to 1.5:1 at 6 ghz. this will be adequate for many applications. if a better input vswr is required, the use of a series inductor, l1 in the applica- tions example, (or, alternatively a length of high impedance trans- mission line) is all that is needed to improve the match. the table in figure 16 shows suggested values for l1 for various wireless fre- quency bands. frequency inductor, l1 (ghz) (nh) 0.9 10 1.5 6.8 1.9 3.9 2.4 2.7 4.0 0.5 5.8 0 figure 16. values for l1. these values for l1 take into account the short length of 50 ? transmission line between the inductor and the input pin of the device. for applications requiring mini- mum noise figure (nf o ), some improvement over a 50 ? match is possible by matching the signal input to the optimum noise match impedance, o , as specified in the typical noise parameters table. for most applications, as shown in the example circuit, the output of the mga-81563 is already sufficiently well matched to 50 ? and no additional matching is needed. the nominal device output vswr is 2.2:1 from 300 mhz through 6 ghz. the completed application amplifier with all components and sma connectors is shown in figure 17. in out +v c4 c3 rfc c2 l1 c1 mga-8-a figure 17. complete application circuit.
8 operation in saturation for higher output power for applications such as pre- driver and driver stages in trans- mitters, the mga-81563 can be operated in saturation to deliver up to 50 mw (17 dbm) of output power. the power added effi- ciency increases to 45% at these power levels. there are several design consider- ations related to reliability and performance that should be taken into account when operating the amplifier in saturation. first of all, it is important that the stage preceding the mga-81563 not overdrive the device. refer- ring to the absolute maximum ratings table, the maximum allowable input power is +13 dbm. this should be regarded as the input power level above which the device could be perma- nently damaged. driving the amplifier into satura- tion will also affect electrical performance. figure 18 presents the output power, third order intercept point (output ip 3) , and power added efficiency (pae) as a function of input power. this data represents performance into a 50 ? load. since the output impedance of the device changes when driven into saturation, it is possible to obtain even more output power with a power match. the optimum impedance match for maximum output power is dependent on frequency and actual output power level and can be arrived at empirically. -20 -5 0 5 -15 -10 10 pout and ip 3 (dbm), pae (%) power in (dbm) -10 0 10 30 20 50 40 power pae ip 3 figure 18. output power, ip 3 , and power-added-efficiency vs. input power. (v d = 3.0 v) as the input power is increased beyond the linear range of the amplifier, the gain becomes more compressed. gain as a function of either input or output power may be derived from figure 18. gain compression renders the amplifier less sensitive to variations in the power level from the preceding stage. this can be a benefit in systems requiring fairly constant output power levels from the mga-81563. increased efficiency (45% at full output power) is another benefit of saturated operation. at high output power levels, the bias supply current drops by about 15%. this is normal and is taken into account for the pae data in figure 18. noise figure and input impedance are also affected by saturated power operation. as a guideline, the input impedance is lowered, resulting in an improvement in input vswr of approximately 20%. like other active devices, the intermodulation products of the mga-81563 increase as the device is driven further into nonlinear operation. the 3rd, 5th, and 7th order intermodulation products of the mga-81563 are shown in figure 19 along with the funda- mental response. this data was measured in the test circuit in figure 10. -30 -5 0 5 10 -15 -10 15 pout, 3rd, 5th, 7th harmonics (dbm) frequency (ghz) -60 -50 -40 -20 -30 30 -10 0 10 20 7th 5th 3rd pout figure 19. intermodulation products vs. input power. (v d = 3.0 v) operation at bias voltages other than 3 volts while the mga-81563 is designed primarily for use in +3 volt applications, the internal bias regulation circuitry allows it to be operated with any power supply voltage from +1.5 to +5 volts. performance of gain, noise figure, and output power over a wide range of bias voltage is shown in figure 20. as can be seen, the gain and nf are fairly flat, but an increase in output power is possible by using higher voltages. the use of +5 volts increases the p 1db by 2 dbm.
9 nf, gain, p 1 db (db) supply voltage (v) 0 2 4 8 6 18 10 12 14 16 nf gain power 0345 12 figure 20. gain, noise figure, and output power vs. supply voltage. some thermal precautions must be observed for operation at higher bias voltages. for reliable operation, the channel tempera- ture should be kept within the 165 c indicated in the absolute maximum ratings table. as a guideline, operating life tests have established a mttf in excess of 10 6 hours for channel tempera- tures up to 150 c. there are several means of biasing the mga-81563 at 3 volts in systems that use higher power supply voltages. the simplest method, shown in figure 21a, is to use a series resistor to drop the device voltage to 3 volts. for example, a 47 ? resistor will drop a 5-volt supply to 3 volts at the nominal current of 42 ma. some variation in performance could be expected for this method due to variations in current within the specified 31 to 51 ma min/max range. 47 ? (a) +5 v silicon diodes (b) +5 v zener diode (c) +5 v figure 21. biasing from higher supply voltages. a second method illustrated in figure 21b, is to use forward- biased diodes in series with the power supply. for example, three silicon diodes connected in series will drop a 5-volt supply to approximately 3 volts. the use of the series diode approach has the advantage of less dependency on current variation in the amplifiers since the forward voltage drop of a diode is somewhat current independent. reverse breakdown diodes (e.g., zener diodes) could also be used as in figure 21c. however, care should be taken to ensure that the noise generated by diodes in either zener or reverse break- down is adequately filtered (e.g., bypassed to ground) such that the diodes noise is not added to the amplifiers signal. sot-363 pcb footprint a recommended pcb pad layout for the miniature sot-363 (sc-70) package used by the mga-81563 is shown in figure 22 (dimensions are in inches). this layout pro- vides ample allowance for pack- age placement by automated assembly equipment without adding parasitics that could impair the high frequency rf performance of the mga-81563. the layout is shown with a nominal sot-363 package foot- print superimposed on the pcb pads. 0.026 0.079 0.018 0.039 dimensions in inches. figure 22. recommended pcb pad layout for agilents sc70 6l/sot-363 products. smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot-363 package, will reach solder reflow temperatures faster than those with a greater mass.
10 time (seconds) t max temperature ( c) 0 0 50 100 150 200 250 60 preheat zone cool down zone reflow zone 120 180 240 300 figure 23. surface mount assembly profile. the mga-81563 is has been qualified to the time-temperature profile shown in figure 23. this profile is representative of an ir reflow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporat- ing solvents from the solder paste. the reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. the rates of change of tempera- ture for the ramp-up and cool- down zones are chosen to be low enough to not cause deformation of the board or damage to compo- nents due to thermal shock. the maximum temperature in the reflow zone (t max ) should not exceed 235 c. these parameters are typical for a surface mount assembly process for the mga-81563. as a general guideline, the circuit board and components should be exposed only to the minimum tempera- tures and times necessary to achieve a uniform reflow of solder. electrostatic sensitivity gaas mmics are electrostatic discharge (esd) sensitive devices. although the mga-81563 is robust in design, permanent damage may occur to these devices if they are subjected to high energy electrostatic discharges. electrostatic charges as high as several thousand volts (which readily accumulate on the human body and on test equip- ment) can discharge without detection and may result in degradation in performance or failure. the mga-81563 is an esd class 1 device. therefore, proper esd precautions are recom- mended when handling, inspect- ing, and assembling these devices to avoid damage.
11 package dimensions outline 63 (sot-363/sc-70) part number ordering information no. of part number devices container mga-81563-tr1 3000 7" reel mga-81563-tr2 10000 13" reel mga-81563-blk 100 antistatic bag mga-81563-tr1g 3000 7" reel mga-81563-tr2g 10000 13" reel mga-81563-blkg 100 antistatic bag note: for lead-free option, the part number will have the character g at the end. e he d e a1 b a a2 q1 l c dimensions (mm) min. 1.15 1.80 1.80 0.80 0.80 0.00 0.10 0.15 0.10 0.10 max. 1.35 2.25 2.40 1.10 1.00 0.10 0.40 0.30 0.20 0.30 symbol e d he a a2 a1 q1 e b c l notes: 1. all dimensions are in mm. 2. dimensions are inclusive of plating. 3. dimensions are exclusive of mold flash & metal burr. 4. all specifications comply to eiaj sc70. 5. die is facing up for mold and facing down for trim/form, ie: reverse trim/form. 6. package surface to be mirror finish. 0.650 bcs
tape dimensions and product orientation for outline 63 device orientation p p 0 p 2 f w c d 1 d e a 0 10 max. t 1 (carrier tape thickness) t t (cover tape thickness) 10 max. b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.25 0.094 0.004 0.094 0.004 0.047 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.10 4.00 0.10 1.75 0.10 0.061 + 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 + 0.30 - 0.10 0.254 0.02 0.315 + 0.012 0.0100 0.0008 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance width tape thickness c t t 5.40 0.10 0.062 0.001 0.205 + 0.004 0.0025 0.0004 cover tape user feed direction cover tape carrier tape reel end view 8 mm 4 mm top view 81 81 81 81 for product information and a complete list of agilent contacts and distributors, please go to our web site. www.agilent.com/semiconductors e-mail: semiconductorsupport@agilent.com data subject to change. copyright ? 2004 agilent technologies, inc. obsoletes 5988-7054e november 15, 2004 5989-1798en

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